In fabrication of semiconductor devices, particularly fabrication of SRAM bitcells, traditional methods utilize fins generated using a single sidewall image transfer (SIT) process. However, traditional single SIT methods may only generate fins having a fin pitch greater than 40 nm. Further, traditional SIT methods generate a constant fin pitch, resulting in an inefficient use of layout area.
A need therefore exists for methodology enabling a generation of fins having a variable fin pitch less than 40 nm, and the resulting device.